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Oracle’s Rick Hetherington Offers a Deep Dive into SPARC T5
Noting that Oracle continues to invest heavily in SPARC processors and systems, Rick Hetherington, Oracle’s vice president of hardware development, recently spoke in detail about the new SPARC T5 processor. In addition to a number of performance improvements, the new processor provides security and power savings enhancements, all while maintaining binary compatibility with Oracle Solaris.
“Oracle’s team of architects and performance analysts is delivering exciting new products in a predictable way as we outlined in our public roadmaps,” Hetherington says. “We value our SPARC customers and appreciate the trust they have in our products, and we will return that trust with a continuous stream of competitive and innovative products.”
In an in-depth interview, Hetherington describes the technical details of the new SPARC T5 processor and offers insights into the internal design process that produced the next-generation processor platform.
SPARC T5 introduces a range of performance improvements over previous designs by building on the 40-nanometer S3 core that was introduced in the SPARC T4 processor. Hetherington says that the doubling of cores increases the SPARC T5’s throughput by more than a factor of two. The latest SPARC processor also increases clock speeds from 3GHz to 3.6GHz and integrates PCI Express Rev 3 on die, for double the I/O bandwidth. Thanks to a greater number of DDR3 on-die memory controllers, memory bandwidth has also doubled.
The SPARC T5 can scale to eight sockets. So with 16 cores, SPARC T5 can interconnect eight sockets for a total of 128 cores. Hetherington explains that each core can support up to eight independent threads or strands, so from an operating system point of view, there are a total of 1024 CPUs. “That means that customers now can take advantage of more than 100 physical SPARC cores, more than 1,000 threads (or CPUs), and many terabytes of physical memory in a modestly sized rackable system,” he adds. “This translates into significant reduction in power consumption and physical space requirements.”
With this large number of cores, memory bandwidth becomes very important. SPARC T5 was designed to support nearly 80 gigabytes of usable memory bandwidth. With nearly linear scaling across eight sockets, SPARC T5 systems exceed half a terabyte per second of aggregate memory bandwidth. This accelerates the performance of virtualized applications that require enormous amounts of memory.
SPARC T5 also features new power management features, and for added security, each core has an encryption engine that will accelerate all the most common bulk encryption ciphers.
Read the full interview with Oracle’s Rick Hetherington.
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