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OpenSPARC Publications

  • Books (7 Articles)
    Books related to OpenSPARC and Chip Multi Threading (CMT).
  • Presentations (32 Presentations)
    Presentations from past events given by Sun Employees and Community Members.
  • Technical Papers (9 Articles)
    The following links are to selected papers Sun has published in some of the top computer architecture conferences. These papers introduce the design challenges motivating chip-multithreading (CMT) processors as well as some of the innovative approaches we have developed. In addition, these research papers indicate how the infrastructure of SPARC systems, tools and traces enables exciting and relevant research in server design.


1OpenSPARC Internals: Download the free PDF David Weaver
2 The Art of Multiprocessor Programming Maurice Herlihy, Nir Shavit
3 Using OpenMP - Portable Shared Memory Parallel Programming Barbara Chapman, Gabriele Jost, Ruud van der Pas
4 Solaris Application Programming Darryl Gove
5 Computer Architecture A Quantitative Approach - Fourth Edition John Hennessy, David Patterson
6 Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency Kunle Olukotun, Lance Hammond, James Laudon
7 Sun BluePrints Book: Techniques for Optimizing Applications: High Performance Computing Rajat P. Garg, Ilya Sharapov, Prentice Hall PTR


# Title Author
1 Slidecasts: All About OpenSPARC Sun Microsystems
1.1 - Chip Multi-Threading (CMT) Era Dave Weaver
1.2 - What is OpenSPARC? Dave Weaver
1.3 - SPARC Architecture Generations Dave Weaver
1.4 - OpenSPARC T1 Overview Denis Sheahan
1.5 - OpenSPARC T2 Overview Denis Sheahan
1.6 - OpenSPARC - What's Available? Tom Thatcher
1.7 - OpenSPARC FPGA Implementation Tom Thatcher
1.8 - OpenSPARC Simulators Stephen Henry
1.9 - Hypervisor and Virtualization Maran Wilson
1.10 - Developing Applications for CMT Processors Darryl Gove
1.11 - Operating Systems for OpenSPARC Darryl Gove
12 RAMP Retreat August, 2008 Update Sun Microsystems
13 ESC 2008: Parallelising serial applications Darryl Gove
14 MultiCore Expo 2008: Multicore Processors and Microparallelism Lawrence Spracklen
15 MultiCoreExpo 2008:Strategies for improving the performance of single threaded codes on a CMT system Darryl Gove
16 MultiCore Expo 2008: Hardware and Software solutions for scaling highly threaded processors Denis Sheahan
17 SNUG08: Verification Patterns in Addition to RVM Carl Cavanagh, Chris Sine and Lee Warner
18 RAMP Retreat January 2008 Update Sun Microsytems
19 HLDVT 07: Post-Silicon Verification Methodology on Sun's UltraSPARC T2 Processor Jai Kumar, Catherine Ahlschlager and Peter Isberg
20 Multicore Expo 2007 - Scaling Down from Chip Multicore to Single Core - The OpenSPARC T1 Experience Durgam Vahia
21 Multicore Expo 2007 - Open Source Hardware - Myth Becomes Reality Fadi Azhari
22 Workshop on Recent Trends in Processor Architecture Ramesh Iyer, Shrenik Mehta, David Weaver, Jhy-Chun Wang
23 ISSCC 2007: An 8-core, 64-thread, 64-bit, power efficient SPARC SoC (Niagara2) U. Nawathe, M.Hassan, L. Warriner, K. Yen, B. Upputuri, D.Greenhill, A.Kumar, H. Park
24 Hot Chips 18: Niagara-2: A Highly Threaded Server-on-a-Chip Greg Grohoski
25 8th EMICRO: Random Test Generators for Microprocessor Design Validation Joel Storm
26 MultiCore Expo 2006: System Implications of Aggressive CMT Processors Rick Hetherington
27 MultiCore Expo 2006: Microarchitecture of the UltraSPARC-T1 CPU Poonacha Kongetira
28 MultiCore Expo 2006: The Parallel Revolution is (Finally) Here: Time to make concurrency RAMPant Prof. David Patterson
29 MultiCore Expo 2006: Maximizing the Benefits of CMT with Sun's Compilers and Tools Partha Tirumalai

Technical Papers

# Title Author
1 IWMSE09: Transparent Multi-core Cryptographic Support on Niagara CMT Processors" Hughes, Morton, Pechanec, Scuba, Spracklen and Yenduri
2 UltraSPARC T2: A Highly-Threaded, Power-Efficient, SPARC SOC Many Authors
3 HLDVT 07: Coverage-directed test generation through automatic constraint extraction Onur Guzey, Li-C. Wang
4 The Landscape of Parallel Computing Research: A View from Berkeley University of Berkeley
6 A Power-Efficient High-Throughput 32-Thread SPARC Processor A. Leon, J. Shin, K. Tam, W. Bryg, F. Schumacher, P. Kongetira, D. Weisner, A. Strong
7 Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults Dong Tang, Peter Carruthers, Zuheir Totari, Michael Shapiro
8 Niagara: A 32-Way Multithreaded SPARC Processor Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun
9 Chip Multithreading: Opportunities and Challenges Lawrence Spracklen, Santosh G. Abraham